1. Field of the Disclosure
The present disclosure pertains to the field of signal transfer between components. More particularly, the present disclosure pertains to source synchronous transmission of signals at various frequency ratios with respect to a core frequency.
2. Description of Related Art
One limitation on throughput of processing in a computer or other processing system is the interconnection between integrated circuits and/or other components in the system. Interconnection circuits also typically consume significant amounts of power and space on the components. Improved interconnect techniques may advantageously allow faster signaling between components thereby increasing system throughput. Improved interconnect techniques may also allow different signaling levels that may either allow faster signaling or may reduce area or power consumption of the signaling circuits.
In some cases, interconnect circuits are unable to transfer data as rapidly as a component produces or requests data. One prior art mechanism for dealing with this problem is to provide a bus interface that operates at a lower frequency than a core portion of the component. For example, a number of Intel Pentium.RTM. Processors have a core frequency that operates at either even fractional multiplier (e.g., a 1:2, 1:3, etc., bus to core frequency ratio) or an odd fractional multiplier (e.g., a 2:3, 2:5, etc., bus to core frequency ratio).
These processors, however, generally do not employ a source synchronous scheme to interface with a general system bus. The interface with the system bus is referred to as a front side bus as some processors employ a back side bus to interface with a cache memory. The front side bus typically employs a clocking scheme where signals are latched and captured with reference to a common system clock signal rather than one which is transferred along with the data or command signals being transferred as is done in a typical source synchronous arrangement.
Prior art processors also include back side buses employing source synchronous signaling. In fact such source synchronous signaling has been accomplished using even fractions of the core clock frequency in processors such as the Intel Pentium.RTM. II processor. Prior art processors, however, may not have implemented an adequate source synchronous interface for high speed operation at a bus frequency that is an odd fraction of the core clock frequency.